Presently, variable frequency converters are widely used in industry fields and are tending to be developed to high voltage, large current, high power density, high reliability and low cost. In high voltage variable frequency field, since the power converter is restricted by the performance of semiconductor components, a NPC three-level topology is generally used.
FIG. 1 is a circuit diagram showing one phase of the circuit of a typical NPC three-level topology. Although FIG. 1 only exemplarily shows one phase of the circuit of a typical NPC three-level topology, for the NPC three-level topology with three phases, the other two phases have the same feature as that of the circuit shown in FIG. 1. In FIG. 1, S1, S2, S3 and S4 are semiconductor components, FWD1, FWD2, FWD3 and FWD4 respectively connected in parallel with S1, S2, S3 and S4 are freewheeling diodes, D1 and D2 are natural point clamping diodes, C1 is capacitor for upper-arm, C2 is capacitor for lower-arm, P is a positive DC (direct current) bus, N is a negative DC bus, NP is a neutral-point bus, and AC is an AC (alternating current) input/output bus.
As shown in FIG. 1, such a NPC three-level topology is characterized in that the voltage stress of each of semiconductor components is reduced by half, comparing with the two-level topology, the number of semiconductor components contained in the power unit increases and the structure thereof becomes more complicated, stray inductance in the power unit increases and can't be ignored any more. In particular, as switching speed of semiconductor components and power output are increasingly improved, stray inductance induces a high voltage when a semiconductor component turns off under normal operation or short-circuit, which may increase voltage stress to the semiconductor component, thereby reducing reliability and even damaging the semiconductor component. Therefore, it is significantly important to appropriately arrange power units so as to reduce stray inductance.
FIGS. 2A-2C is circuit diagrams showing an example of a method for reducing an influence of voltage induced by stray inductance on a semiconductor component in a conventional neutral-point clamp three-level topology.
As shown in FIGS. 2A-2C, in the art, in order to reduce the influence of voltage induced by stray inductance in NPC three-level topology on semiconductor components, a conventional method adds a snubber circuit (clamping circuit) connected in parallel with semiconductor component, and the typical snubber circuit is R, RC, RCD, and so on. When a semiconductor component S1 is turned off, energy existing on stray inductance is absorbed by an energy-storage element in the snubber circuit, and thus the voltage across the semiconductor component S1 can be suppressed. Although this method can reduce the influence simply and effectively, when S1 is turned on, energy absorbed by the snubber circuit is released through S1, which leads to additional turned-on loss and deteriorates dynamic performance of semiconductor components. In addition, since additional high voltage devices are added, the converter has disadvantages of an increased failure rate, a reduced power density, an improved cost, and so on.
Presently, another method for reducing stray inductance is laminated busbar. The laminated busbar has advantages of small stray inductance and effective suppression of EMI (Electro Magnetic Interference), and so on. Therefore, laminated busbars are widely applied to large power frequency conversion field.
In order to reduce stray inductance, laminated busbar should supply path that makes currents through respective layers of conductor parts take on mirror symmetry. The higher the symmetry is, the smaller the area of the current commutation loop in the conductor part is and the less the magnetic flux is in case of constant flux density, and thus the less the stray inductance is. Although stray inductance can be approximately ignored when laminated busbar used, some other problems still exist in such laminated busbars in the art. For example, particularly in the NPC three-level circuit, since the number of components increases, and the area of components itself increases, multiple layers of laminated busbars are required to achieve so complicated electrical connection, and the manufacturing cost of such multiple layers of laminated busbars becomes high. In addition, as the layer number of busbars increases, stray inductance increases due to the increasing thick of insulating layers located between layers, and the insulating process between layers becomes more complicated.
For example, U.S. Pat. No. 6,456,516B1, titled as “Provision of a low-inductive rail for three-point phase module”, discloses a laminated busbar structure. The laminated busbar proposed by this patent document is designed as three layers of laminated busbars, and may be extended to a NPC three-level topology having N semiconductor switching components in series connection. Although stray inductance is reduced to some extent in this patent, the laminated busbar in this patent is still a busbar with multiple layers, and thus corresponding thick of insulating layers need to be interposed between every two layers by an insulating process, which leads to the laminated busbar thick as a whole and causes the reduction in stray inductance depending on the thick of the insulating layer. In addition, in this patent, the shapes of respective sub busbars are different from each other, and it is required to process bends and steps with different depths in respective layers so as to connect each of layer of busbar with corresponding pins of semiconductor components, which makes the manufacturing process of busbar complicated, and it is necessary to make adherence processing between the respective busbars so as to avoid gaps between laminated layers due to bending of busbar. Therefore, the electrical performance of such busbar structure is weak and counts against cost optimization.
Similarly, another U.S. Pat. No. 7,881,086B2, titled as “Power conversion device and fabricating method for the same” discloses a laminated busbar structure. The laminated busbar proposed by this U.S. Pat. No. 7,881,086B2 also comprises a busbar with multiple layers (4 layers). Thus, there exist such problems that the layer number of busbars is too many to weaken the effect of the realization of low stray inductance, it is required to process different holes since the shapes of respective sub busbars are different from each other, and too many laminated layers needs to more holes (more through holes). Therefore, the laminated busbar proposed by this patent is also complicated and counts against cost optimization.